Verification outgrew the design.
The headcount didn’t.

chipstep works on RTL and verification: the SystemVerilog, the UVM environment around it, the constrained-random regressions, the long grind to coverage closure. Every process node makes the design bigger, and the verification that has to cover it grows faster still. Teams do not grow at that rate. Nobody’s does.

We are building an agent for that work. We are keeping quiet about it for now. We would rather show nothing than show something we haven’t built.